We propose 6 excellent half-day (3 hours long) TUTORIALs on Sunday 23rd June 2019, covering the broad interests in the scope of Circuits and Systems design:

Sunday June 23rd
9:00 – 12:30
T1: Systematic design of low-power Analog/RF CMOS circuits using the Inversion Coefficient T2: Spread-spectrum techniques for mitigation of inband jammers in RF transceivers T3: An Efficient Solution to Simulate Mixed-Signal Circuits in C
Prof. Christian Enz, EPFL,
Prof. Willy Sansen, KU Leuven
Prof. Thierry Taris, University of Bordeaux
Prof. Ramesh Harjani, University of Minnesota, USA Yves Leduc, PhD, Hdr, Associate member, Polytech Lab, University of Nice Sophia-Antipolis, France
Sunday June 23rd
14:00 – 17:30
T4: Amplifier Efficiency vs Linearity: what physics does and does not allow? T5: Things you always wanted to know about the bioelectricity of living cells and their marriage with electronics – but never dared to study T6: Design and mitigation methodologies of COTS FPGAs for Aerospace Missions
Prof. Dr. Earl McCune, TU Delft Prof. Dr. Joachim Wegener, Fraunhofer EMFT
Prof. Dr. Sven Ingebrandt, RWT Aachen
Assoc. Prof. Luca Sterpone, Politecnico di Torino, Italy


Fraunhofer Haus, Hansastrasse 27c, 80686 Munich

This event takes place at the premises of Fraunhofer EMFT, access via the front desk of Fraunhofer Haus (see here).

Due to the limitation of room capacity, we offer the TUTORIALs on the FIRST-COME FIRST-SERVE basis. Therefore, hurry up to register before all of them are booked!

Please check the program for the exact timing as this may slightly change until the full program, completed with regular sessions is published in April 2019.

Tutorial 1: Systematic design of low-power Analog/RF CMOS circuits using the Inversion Coefficient


  • Prof. Christian Enz, École polytechnique fédérale de Lausanne, Switzerland
  • Prof. Willy Sansen, Katholieke Universiteit Leuven, Belgium
  • Prof. Thierry Taris, University of Bordeaux, France  


The emergence of the Internet of Things (IoT) poses stringent requirements on the energy consumption and has hence become the primary driver for low-power analog and RF circuit design. Implementation of increasingly complex functions under highly constrained power and area budgets, while circumventing the challenges posed by modern device technologies, makes analog and RF circuit design ever more challenging. Some guidance would therefore be invaluable for the designer to navigate the multi-variable design space. 

This tutorial presents low-power analog and RF design techniques that can be applied from device to circuit level. It starts with the presentation of the concept of inversion coefficient 𝐼𝐶 as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion. Several figures-of-merit (FoM) including the Gm/Id, the Ft and their product Gm*Ft/Id, capturing the various trade-offs encountered in analog and RF circuit design are presented. The simplicity of the 𝐼𝐶-based models is emphasized and compared against measurements of 40- and 28-nm bulk CMOS processes and BSIM6 simulations.

The reduction of power consumption at a given frequency is achieved not only by proper biasing, but also by dedicated circuit techniques. This reduction in power consumption will become even more important as CMOS scales down to 5-nm. Of the circuit techniques to be examined, the cancellation of parasitic capacitances is the first. It is followed by the use of negative resistors for both higher gain and higher speed. Then, the cancellation of poles by zeros in multistage amplifiers and by use of feedforward is discussed. Finally, cancellation techniques for noise and distortion will follow.  

The challenge related to the design of RF CMOS building blocks concerns the technology, the circuit topology and the synthesis to address a set of specifications defined by the application. To address it a 3-step design methodology based on the Inversion Coefficient is proposed. Integrated in a design interface the methodology is exploited to develop RF Low Noise Amplifiers (LNA). Two applications are further considered: Wide Band Inductorless LNA for multi-mode/multi-standard Radio applications, and Ultra Low Power LNA dedicated to 2.4GHz Wireless Sensor Networks. Four LNA topologies designed in three technology nodes (130nm, 65nm and 28nm) are compared and discussed.

The tutorial is organized in 3 parts: 

  1. Transistor-level operating point optimization using the inversion coefficient and various FoMs
  2. Circuits level power optimization using cancelation techniques
  3. RF circuit design with the inversion coefficient: Application to LNA Implementation

Prof. Christian EnzProf. Christian ENZ, PhD, Swiss Federal Institute of Technology (EPFL), 1989. He is currently Professor at EPFL and Director of the Institute of Microengineering (IMT) and head of the IC Lab. Until April 2013 he was VP at the Swiss Center for Electronics and Microtechnology (CSEM) in Neuchâtel, Switzerland where he was heading the Integrated and Wireless Systems Division. Prior to joining the CSEM, he was Principal Senior Engineer at Conexant (formerly Rockwell Semiconductor Systems), Newport Beach, CA, where he was responsible for the modeling and characterization of MOS transistors for RF applications. From 1992 to 1997, he was an Assistant Professor at EPFL, working in the field of low-power analog CMOS IC design and device modeling. In 1989 he was one of the founders of Smart Silicon Systems S.A. (S3), where he developed several low-noise and low-power ICs, mainly for high energy physics application at CERN. His technical interests and expertise are in the field of ultra-low-power analog and RF IC design, wireless sensor networks and semiconductor device modeling. Together with E. Vittoz and F. Krummenacher he is the developer of the EKV MOS transistor model and the author of the book "Charge-Based MOS Transistor Modeling - The EKV Model for Low-Power and RF IC Design" (Wiley, 2006). He is the author and co-author of more than 220 scientific papers and has contributed to numerous conference presentations and advanced engineering courses.

He is an IEEE Fellow and an individual member of the Swiss Academy of Engineering Sciences (SATW). He has been member of several technical program committees, including International Solid-State Circuits Conference (ISSCC) and European Solid-State Circuits Conference (ESSCIRC). He has served as a vice-chair for the 2000 International Symposium on Low Power Electronics and Design (ISLPED), exhibit chair for the 2000 International Symposium on Circuits and Systems (ISCAS) and chair of the technical program committee for the 2006 European Solid-State Circuits Conference (ESSCIRC).

He has been an elected member of the IEEE Solid-State Circuits Society (SSCS) Administrative Commmittee (AdCom) from 2012 to 2014 and the Chair of the IEEE Solid-State Chapter of West Switzerland.

Link: https://people.epfl.ch/cgi-bin/people?id=105059&op=bio&lang=en&cvlang=en

Prof. Willy SANSEN has received the MSc degree in Electrical Engineering from the Katholieke Universiteit Leuven in 1967 and the PhD degree in Electronics from the University of California, Berkeley in 1972.

In 1972 he was appointed by the National Fund of Scientific Research (Belgium) at the ESAT laboratory of the K.U.Leuven, where he has been a full professor since 1980. During the period 1984-1990 he was the head of the Electrical Engineering Department. Between 1984 and 2008 he has headed the ESAT-MICAS laboratory on analog design, which counts about sixty members and which is mainly active in research projects with industry. He was involved in spinoffs such as Ansem, ICSense, Kimotion, Zenso and is a member of several boards of directors.  

In 1984 he was involved in the creation of IMEC, in which he was consultant up to 2008.

In 1978 he was a visiting professor at Stanford University, in 1981 at the EPFL Lausanne, in 1985 at the University of Pennsylvania, Philadelphia, in 1994 at the T.H. Ulm, in 2004 at Infineon, Villach and in 2012 at the Technical University Munchen.

Prof. Sansen is a member of several editorial and program committees of journals and conferences. He is cofounder and organizer of the workshops on Advances in Analog Circuit Design in Europe. He was a member of the executive and program committees of the IEEE ISSCC conference from 1995 to 2009. He was program chair of the ISSCC-2002 conference and President of the Solid-State Circuits Society in 2008-2009. He is recipient of the SSCS Donald Pederson Award in 2011. He is a Life Fellow of the IEEE.

He has been involved in design automation and in numerous analogue integrated circuit designs for telecommunications, consumer electronics, medical applications and sensors. He has been supervisor of over sixty-five PhD theses in these fields. He has authored and coauthored more than 660 papers in international journals and conference proceedings and sixteen books among which the slide based book “Analog Design Essentials” (Springer 2006).

Prof. Thierry TARISProf. Thierry TARIS received his Master and PhD degrees from the University of Bordeaux (UB), France, in 2000 and 2003 respectively. He joined the IMS Lab in 2005 as an Associate Professor of UB, and then the Bordeaux Institute of Technology (Bx-INP) in 2014 as a full Professor. His research interests are related to the Radio-Frequency Integrated Circuits in Silicon technologies. More specifically, it concerns the design of Low Noise Amplifiers and Mixers, the development of wake-up radio and RF energy harvesters.

Since 2008 he has been enrolled as a coordinator and/or scientific contributor for more than 14 European (MEDEA+, ENIAC program) projects and National (ANR RNRT, FUI, CIFRE, Région Aquitaine) projects. He has published more than 100 papers in international journals and conferences, 3 Best Paper Awards and is co-inventor of 6 patents.

Prof. Taris has led the circuit design group from 2011 to 2014. He was an invited Professor of the University of British Columbia (UBC), Vancouver, Canada, in 2012 and 2014, and Ecole Polytechnic Federal de Lausanne (EPFL), Lausanne, Switzerland, in 2016. For 6 years Dr. Taris has been a board member of the ST-IMS joined lab between the IMS lab and ST-Microelectronics. From 2016 he is an expert for the Strategic Business Area (SBA) of Aerospace Valley, one of the largest Competitiveness Cluster for Aeronautics, Space and Embedded Systems in Europe.

Tutorial 2: Spread-spectrum techniques for mitigation of inband jammers in RF transceivers

Speaker: Prof. Ramesh Harjani, University of Minnesota, USA

Spread-spectrum techniques have traditionally been used in the digital basedband’s of RF transceivers to provide multiple access and/or improved jammer resilience. In this tutorial, we examine and present spread-spectrum techniques operated at RF to provide inband jammer resilience. Mixer-first N-path filters have shown significant success in rejecting out-of-band jammers before entering the active receiver signal path. In this talk we will focus on the use of mixer-first N-path filters that use spread-spectrum techniques to reject in-band jammers. We will explore both DSSS and FHSS spectrum techniques and consider how such techniques inherently provide 10*log(N) jammer rejection. We then consider specific implementations of both DSSS and FHSS spread-spectrum techniques. In particular, we discuss two DSSS implementations, one that provides 20dB of in-band jammer resistance and another that uses Walsh code encrypted N-path filters to provide nearly 40dB of self-interference rejection. Finally, we will focus on the use of N-path filters for ultra-fast hopping transceivers that provide processing gain and jammer rejection of in-band jammers.

Prof. Ramesh HarjaniProf. Ramesh Harjani is the E.F. Johnson Professor of Electronic Communications in the Department of Electrical & Computer Engineering at the University of Minnesota. He is a Fellow of the IEEE. He received his Ph.D. in Electrical Engineering from Carnegie Mellon University in 1989. He was at Mentor Graphics, San Jose before joining the University of Minnesota. He has been a visiting professor at Lucent Bell Labs, Allentown, PA and the Army Research Labs, Adelphi, MD. He co-founded Bermai, Inc, a startup company developing CMOS chips for wireless multi-media applications in 2001. Dr. Harjani received the National Science Foundation Research Initiation Award in 1991 and Best Paper Awards at the 1987 IEEE/ACM Design Automation Conference, the 1989 International Conference on Computer-Aided Design, and the 1998 GOMAC. His research group was the winner of the SRC Design Challenge in 2000 and 2003. He was the Technical Program Chair for the IEEE Custom Integrated Circuits Conference 2012-2013, the Chair of the IEEE Circuits and Systems Society technical committee on Analog Signal Processing 1999-2000 and a Distinguished Lecturer of the IEEE Circuits and Systems Society 2001-2002. He was an Associate Editor for IEEE Transactions on Circuits and Systems Part II, 1995-1997, Guest Editors for the International Journal of High-Speed Electronics and Systems and for Analog Integrated Circuits and Signal Processing in 2004 and a Guest Editor for the IEEE Journal of Solid-State Circuits, 2009-2011. He was a Senior Editor for the IEEE Journal on Emerging & Selected Topics in Circuits & Systems (JETCAS), 2011-2013. He has given several plenary and keynote lectures at IEEE conferences. His research interests include analog/RF circuits for wireless communication systems.

Tutorial 3: An Efficient Solution to Simulate Mixed-Signal Circuits in C  

Speaker: Yves Leduc, PhD, Hdr, Associate member, Polytech Lab, University of Nice Sophia-Antipolis

High-level modeling is essential in the design of advanced mixed-signal circuits. The designer is searching not only for speed, but to comfort his understanding of complex systems and to extract the specifications of the sub-circuits he will eventually have to build.

Serious modeling is not for a dilettante. It needs a solid know-how in the field of the application and a solid expertise in the organization of the test. A good designer is not comfortable with black boxes sold by EDA companies. He expects to understand exactly what is inside the models, what is not, and how the numerical computations are handled. The designer wants to be the pilot, but does not want to loose his time in the picky details of software programming.

Our target is a software for the modeling and simulation of sampled-data digital and analog systems.

We have chosen to use ANSI-C as the programming language. It is a solid-standard; it is very fast and very versatile. We have built a netlist compiler producing on the fly optimized C software codes, which are compiled and executed immediately. It is therefore a compiler of simulators. The language (called NAPA) is designed to describe mixed-signal circuits in a naturally streamlined netlist. The compiler provides a maximum of help to the designer by removing a lot of superfluous declarations while maintaining a strict control about the validity of the description. The designer has a fully access to the documented and formatted C code produced by the NAPA compiler.

The first version of the NAPA compiler was built in 1989 to respond to a strong demand to speed-up significantly the design of the first commercial sigma-delta converters to beat competition.

The code produced by the compiler has many original features. NAPA was conceived to be easily extended and to be fully open to host the functions written by the users. For 30 years, NAPA was enhanced and never failed to respond and sometimes to precede the demand of the users. Many cells, cell generators and functions have been collected making the NAPA environment a repository of best solutions in terms of activation, analysis tools and subsystem cells.

We propose to share the expertise we have built during these years. We will explain the structure of the software and we will detail the key features that make such compiler of simulators a powerful and safe solution. We will show how a set of simple rules in the construction of this compiler guarantee the full extensibility. We will first run NAPA on simple examples to comfort the understanding of the compiling process. A few more elaborate examples on practical subsystems will be run. A full exercise on a sigma-delta converter will conclude the tutorial. The attendees will be encouraged to load the software and play with this example on their personal computers (running Windows 64 bits).  

Its is important to note that NAPA and its ancillary software modules are all freeware!  

Yves LeducYves Leduc was born in Charleroi (Belgium) in 1951. He received his Phd in Electronic Engineering from the Catholic University of Louvain in Louvain-la-Neuve (Belgium) in 1979 and his HDR from Polytech Lab of University of Nice Sophia-Antipolis (France) in 2014. Yves joined Texas Instruments France in 1980, and was elected TI Fellow in 1998.

Yves has participated actively to the migration to analog CMOS and contributed to the first successes of TI in mixed signal. He started immediately to promote and develop original methods and software solutions for the design of mixed-signal systems.

In 1990, he was sent for 18 months to the central research labs of Dallas to share the know-how in Sigma-Delta converters. In 1993, Yves created the mixed-signal design team of TI France. The team made the first mixed signal IC companions to the digital signal processors and contributed to the success of TI in the wireless telecommunication business.

From 2001 to 2011, Yves was the head of a team in charge of advanced system technologies with the responsibility to identify and solve the difficulties that the designers will eventually meet in their works. He proposed the digital modulation of VCO which was the keystone of the 'Digital Radio Processors' of TI, and the 'Smart Reflex' concept combining DVFS and calibration in a novel design methodology of SOCs. During his career, Yves presented numerous conferences and tutorials in many TI locations worldwide and in national and international conferences. Yves was also teaching analog and mixed-signal design for the last 20 years at the University of Nice Sophia-Antipolis.

Tutorial 4: Amplifier Efficiency vs Linearity: what physics does and does not allow?

Speaker: Prof. Dr. Earl McCune, TU Delft

Communications on both wires and wireless has a century of history fighting the tradeoff between providing acceptable linearity for needed signal quality and the power drawn (and paid for) to get that performance. Recent improvements in understanding this trade-off are presented which show more clearly, what is not only possible to achieve, but also how to achieve it.

Having more than 45 years of experience in RF/wireless design and technology development, I have seen a lot of what does work – and what does not. More importantly, I understand how cost relates with communications performance. With the experience of co-founding two start-up companies – both of which succeeded to liquidity events – my ability to contribute extends well beyond technical issues, including: intellectual property portfolio development, product business startup strategies and all aspects of project, technology development, operations, and company leadership. My independent RF laboratory is extensive and is regularly updated. Phase noise, jitter, and frequency synthesizer dynamics measurement are a particular specialty. In my efforts now to “give back” to the industry I have enjoyed working with for so long, I have written two reference books with Cambridge University Press, one on digital modulation (using physics, and not math, as the window onto this material), and the second on dynamic power supply transmitters (envelope tracking, direct polar, and hybrid combinations). I also teach short courses on several topics.
Link(s): http://elca.tudelft.nl/People/bio.php?id=407 ; http://wirelessandhighspeed.com/

Tutorial 5: Things you always wanted to know about the bioelectricity of living cells and their marriage with electronics – but never dared to study


  • Prof. Dr. Joachim Wegener, Fraunhofer EMFT, Germany
  • Prof. Dr. Sven Ingebrandt, RWTH Aachen, Germany

Cells are the fundamental building blocks of life. From less than 1um to several 100um in size they all share the inherent capability of complete self-reproduction at very different rates ranging from several minutes to days. The mechanisms of reproduction are similar among the different cell types but not identical. Cells from unicellular organisms (bacteria, funghi) or assemble to tissues and organs in multicellular organisms like ourselves. In multicellular organisms, cells have evolved very efficient and complex mechanisms to communicate with each other and exchange information even across long distances. This intercellular communication is vital to the functionality of the organism. The cell interior is separated from the environment by a highly functional semipermeable membrane that controls the exchange of matter between intra- and extracellular space. This dielectric membrane is highly permeable to gasses like oxygen and carbon dioxide or small-uncharged molecules like water but hardly permeable to inorganic ions and macromolecules. For the latter, the cell integrates transport systems into the membrane by which it strictly controls the passage of these materials into the cell or out of the cell. The cell surface is also the site where cells present and enormous number of different, physical and biological changes. For the most part, these receptors are proteins that span the membrane. Once they get activated by their individual trigger, the signal is relayed into the cell, integrated and processed intracellularly to provide an orchestrated and balanced cell response. Higher cells not only have a membrane to separate themselves from the extracellular environment, they also from an intracellular membrane system to form individual compartments inside the cell to allow different metabolic reactions to occur and to be regulated independently. Also these inner membranes are semipermeable and passage of ions and molecules is highly controlled.

Bioelectricity forms the basis for cell communication and is also key element of energy conversion in fundamental cell metabolism. The structural basis for bioelectricity is the inner and outer membrane system as it allows separating, accumulating and controlling the flux of charged chemical species. The physiological membrane of a living cell is a battery just as much as a biochemical transistor and an integrated circuit. This tutorial will introduce the cell with respect to its active and passive electrical properties. It will address how electricity and electric circuitry is used by mother nature to sustain life and to control cellular processes. Besides these fundamental aspects, we will address the physical tools and devices that are used to study the underlying principles, screen for ways to interfere with them (e.g. with drugs) and manipulate them for biomedical purposes.

Joachim WegenerJoachim Wegener received his doctorate in 1998 from the University of Muenster and continued his scientific education as a postdoctoral fellow with Prof. Ivar Giaever (Nobel Laureate in Physics) at Rensselaer Polytechnic Institute in Troy (NY). In 2004 he obtained his “Habilitation” at the University of Muenster, Germany. Since 2008 he is full professor for bioanalysis at the University of Regensburg (Germany). His research interests focus on interfacing animal cells with physical transducers (e.g. planar electrodes, piezoelectric devices, …) to monitor the cell response to chemical, biological or physical stimuli without using any labels. It is the paradigm of his research to replace classical concentration-analysis by effect-analysis on biological organisms.

Besides his affiliation with the University of Regensburg, he is head of the division ‘Cell-based Sensors’ of Fraunhofer EMFT.

He was awarded the Transfer Price of the University of Muenster for bringing electro-analytical instrumentation to the marketplace and founded the conference series IBCA (Impedance-based cellular Assays) in 2011. Joachim Wegener is editor-in-chief of the Springer book series Bioanalytical Reviews.  

Link: http://www-analytik.chemie.uni-regensburg.de/wegener/wegener.htm

Prof. Dr. Sven Ingebrandt, RWTH Aachen, Germany
Biography to be updated.

Tutorial 6: Design and mitigation methodologies of COTS FPGAs for Aerospace Missions

Speaker: Assoc. Prof. Luca Sterpone

FPGAs components are used in increasing quantities in both platform avionics and payload instruments. Recently, the European Cooperation for Standardization (ECSS) has defined a particular standard for the Commercial electrical, electronic and electromechanical FPGA component in order to define the level of evaluation, screening and inspection necessary under radiation conditions. The tutorial covers aspects such as Performance (MFLOPs, MIPS, Fmax), Area (LUTs, DFFs), Configurability/Programmability (Needed? Which granularity?), Reliability (Lifetime and static test), Radiation hardness (TID, SEUs, SETs, SEFIs, SEL and SEGR) and quality, packaging, mounting and finally commercial regulation such as ITAR/EAR. The content of the tutorial includes also data showing the different FPGA “eras” based on their architecture used in space ranging from the FPGA fabric to SoC FPGA.

Luca SterponeLuca Sterpone received the MS degree in Computer Engineering (2003) and the PhD degree in Computer and System Engineering (2007) from Politecnico di Torino, Italy. He has been technology transfer engineer at Boeing Satellite Systems, El Segundo, CA (USA) in 2006 and 2007 and technology transfer engineer at EADS, Suresnes - Paris (France) in 2008. Since November 2014 Luca Sterpone is Associate Professor of the CAD and Reliability group at the DAUIN department of Politecnico di Torino.



Luca's research interests include:

  • Reconfigurable Computing-oriented Physical Design
  • Computer-Aided Design Algorithms
  • Fault Tolerance Architectures
  • Radiation Effects on Component and Systems

Luca is the author of more than 170 papers and he received several awards for his research activity such as the Best Paper award at the IEEE European Test Symposium (2005), the EDAA Outstanding Dissertation Award in 2007, the SMACD 2018 Best EDA Tool and the ACM ARC 2018 Best Paper award. He has been Program Co-chair of HiPEAC Reconfigurable Computing Workshop (2012) and General Chair of HiPEAC WRC (2013). He serves as member within the Program Committee of several events such as RADECS, NSREC, ISIE. He has an active collaboration with several companies: Xilinx, Actel, European Space Agency (ESA), Boeing Satellite Systems, Thales Alenia Space, EADS.

Since 2016 Luca Sterpone is an invited speaker of SERESSA – International School on the Effects of Radiation on Embedded Systems for Space Applications.

Link: http://staff.polito.it/luca.sterpone/

Original Call for Tutorials can be reached here.  


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by January 10, 2019
AUTHORS’ SCHEDULE full paper submission:
EXTENDED BY February 24, 2019 (GMT-0700)


Tutorials, June 23, 2019
early registration by May 17, 2019
Conference, June 24 – 26, 2019
early registration by May 17, 2019


Dr ès sc. Erkan Isa
Fraunhofer EMFT
+49 172 246 13 64

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